1. Field of the Invention
The present invention relates to a method for verifying logic behavior of a semiconductor integrated circuit. More specifically, it relates to a simulation system, a simulation method and a simulation program for verifying logic behavior of a semiconductor integrated circuit by dividing the logic behavior into hardware-based logic behavior and software-based logic behavior.
2. Description of the Related Art
The duration of logic behavior verification for designing a large scale integrated circuit (LSI) with increased scale and complexity has been increasing. In addition, to improve reliability of such logic behavior verification, it is necessary to increase verification speed, verify in an upper level design, and verify by using an actual devices or functional blocks.
There is an LSI logic behavior simulation method using highly abstract behavior models, which allow high-speed analysis and logic behavior verification in early stages of design. More specifically, firstly, LSI logic behavior is divided into hardware-based logic behavior and software-based logic behavior. The hardware-based logic behavior is simulated using actual hardware. The software-based logic behavior is simulated using software simulator. Secondly, the hardware-based logic behavior is written using highly abstract behavior models. Afterwards, the logic behavior is verified using the highly abstract behavior models.
Alternatively, LSI logic behavior simulation using a reprogrammable semiconductor device, such as a field programmable gate array (FPGA), has been increasingly used as a logic behavior verification method. More specifically, a logic circuit exhibiting the hardware-based logic behavior of LSI logic behavior is configured in the FPGA. Behavior models for software-based logic behavior are written in C/C++ language or the like. A behavior analyzing unit that simulates logic behavior of behavior models is electrically connected to a circuit board on which a logic circuit configured FPGA is mounted, thereby carrying out LSI logic behavior simulation. In the following, logic behavior simulation using behavior models written in C/C++ language and a logic circuit configured in the FPGA is referred to as ‘collaborative simulation’. Logic behavior simulation using FPGA can detect, in an early stage, malfunctions that will occur when using actual components. There are two collaborative simulation methods:
(1) Software-based logic behavior is written as behavior models operating in sync with an operating clock. The collaborative simulation is then carried out while synchronizing the operating clock for the behavior models with the operating clock of the logic circuit configured in the FPGA and transferring data between the logic circuit and the behavior models.
(2) Software-based logic behavior is written as behavior models not operating in sync with the operating clock. An interface circuit for data transfer between the logic circuit and the behavior models is configured in the FPGA. The collaborative simulation is carried out using the behavior models, the logic circuit, and the interface circuit for data transfer.
Since the method (1) does not need to generate the interface circuit, no time is spent for initiating the collaborative simulation. However, collaborative simulation speed is slow due to limits of the operating clock speed for the behavior models. On the other hand, collaborative simulation speed is faster according to the method (2). However, substantial labor is required to generate the interface circuit.